마이크로프로세서에 연결 가능한 CMOS LCD 디코더-구동회로의 설계

Abstract

마이크로프로세서에 연결 가능한 LCD 디코더-구동회로를 3㎛ CMOS 단일 금속층 설계규칙에 따라 표준셀방식으로 설계하였고 부분적으로 PLA 설계기법으로 설계하였다.

이 회로는 입력부, 디코더-구동부, LCD 후면 구동부의 3부분으로 나누어 구성하였으며, 각각의 기능블럭에 대한 논리시뮬레이션은 EDAS-P를 사용하여 검증하였으며, 회로시뮬레이션은 PSPICE를 사용하여 수행하였다. 칩 면적을 줄이기 위해 4-7 디코더 회로는 PLA 구조를 사용하여 코드 B 형식으로 4-비트 데이터를 7-세그먼트 표시로 디코딩하도록 설계하였다. 본 회로는 2개의 전원 핀을 포함하여 40개의 핀이 필요하다.

설계한 레이아웃 CIF 파일을 마스크 제조 웨이퍼가공 공정을 위해서 ETRI의 3㎛ CMOS 공정라인에 의뢰하였다. 제작된 칩의 기능시험 결과는 ETRI 공정라인의 불안정성으로 전체적 기능은 동작하지 못하였다.

A CMOS LCD decoder - driver LSI interfacable to the microprocessor is designed by the standard cell design method of three major parts ; input, decoder-driver and backplane driver. Each functional block is simulated by using EDAS-P for logic and by PSPICE for circuit. The number of bonding pads of the circuit is forty. The four-to seven decoder circuit for decoding the 4-bit data into a code B format is designed by using a PLA structure in order to reduce the chip area.

The resulting layout CIF file was sent to 3㎛ CMOS process line of ETRI for processing the mask and fabrication. Unfortunately, the function test of fabricated chip was impossible because the process line was very unstable and even the basic inverter circuit was not functioned properly.

A CMOS LCD decoder - driver LSI interfacable to the microprocessor is designed by the standard cell design method of three major parts ; input, decoder-driver and backplane driver. Each functional block is simulated by using EDAS-P for logic and by PSPICE for circuit. The number of bonding pads of the circuit is forty. The four-to seven decoder circuit for decoding the 4-bit data into a code B format is designed by using a PLA structure in order to reduce the chip area.

The resulting layout CIF file was sent to 3㎛ CMOS process line of ETRI for processing the mask and fabrication. Unfortunately, the function test of fabricated chip was impossible because the process line was very unstable and even the basic inverter circuit was not functioned properly.