압저항형 스마트 실리콘 압력 센서의 설계

Abstract

압저항형 스마트 실리콘 압력 센서를 0.6 ㎛ 이중 폴리 실리콘 이중 금속 CMOS 공정으로 구현하기 위하여 설계하였다. 이 스마트 실리콘 압력 센서는 압저항형 저항기들로 된 휘스톤 브리지를 갖는 다이아프램과 op-amp, A/D 변환기, 및 UART 회로 등의 주변회로 들로 구성되어 있다.

브리지 회로의 출력 전압과 압력에 의한 기계적 응력 사이의 관계를 COSMOS-M 상용프로그램으로 다이아프램의 응력 분포를 모의실험하여, 압저항기의 최적의 위치와 크기에 대한 연구를 하였다.

CMOS op-amp 회로는 규정된 출력 특성을 얻기 위하여 크기가 다른 트랜지스터들로 설계하여 HSPICE로 모의실험하여 최적화 시켰다. A/D 변화기 회로는 가능한 칩 면적을 줄이기 위하여 서브 레인징 기법과 신경 MOSFET 구조를 이용하여 설계하였다. UART회로는 VHDL 소스 코드와 셀 라이브러리를 이용하고 Synopsys로 합성하여 설계하였다. 회로의 물리적 레이아우트 설계는 Mentor 틀로 설계하였다. 그러나 온도보상회로와 출력오프셋 문제는 아직 해결하지 못하고 다음에 연구할 예정이다.

A piezoresistive smart silicon pressure sensor is designed to implement with 0.6 ㎛ double-polysilicon double-metal CMOS precess. This smart pressure sensor is composed of a diaphragm with piezoresistive resistors' Wheatstone bridge and the peripheral circuitry of op-amp, A/D converter and UART.

The relationship between the output voltage of the bridge circuit and the mechanical stress by applied pressure was studied by simulating the stress distribution on the diaphragm with COSMOS-M package program to optimize the size and position of piezoresistors.

The CMOS op-amp circuit was designed with different CMOS transistor sizes to obtain the defined op-amp output characteristics and simulated with HSPICE. The A/D converter was designed using neuron MOSFET structure and sub-ranging method to minimize the chip area. The UART circuit was designed by using VHDL source code and cell library and by synthesizing with Synopses and the physical layout of the circuit was designed with Mentor tools. The problems for temperature compensation and the output voltage offset were not yet considered.

A piezoresistive smart silicon pressure sensor is designed to implement with 0.6 ㎛ double-polysilicon double-metal CMOS precess. This smart pressure sensor is composed of a diaphragm with piezoresistive resistors' Wheatstone bridge and the peripheral circuitry of op-amp, A/D converter and UART.

The relationship between the output voltage of the bridge circuit and the mechanical stress by applied pressure was studied by simulating the stress distribution on the diaphragm with COSMOS-M package program to optimize the size and position of piezoresistors.

The CMOS op-amp circuit was designed with different CMOS transistor sizes to obtain the defined op-amp output characteristics and simulated with HSPICE. The A/D converter was designed using neuron MOSFET structure and sub-ranging method to minimize the chip area. The UART circuit was designed by using VHDL source code and cell library and by synthesizing with Synopses and the physical layout of the circuit was designed with Mentor tools. The problems for temperature compensation and the output voltage offset were not yet considered.