테스트가 용이한 RAM의 설계 및 레이아웃에 관한 연구

Abstract

효과적인 고집적 RAM테스팅을 위해 BIST(Built-In Self Test)기법으로 메모리 내부에 테스트 회로를 부가하여 테스??할 수 있도록 하였는데, 이때 고집적 메모리에 가장 효율적인 PSFs(Pattern Sensitive Fault) 검출 알고리듬을 적용하였다. 128가지의 Gray Code의 테스트 패턴과, 타일링을 위한 4개의 기본셀을 바탕으로 한 행에 대해서 전체 비트라인으로 쓰기와 읽기동작을 하고 에러가 발생하면 외부의 핀을 통해 신호를 전달하게 함으로써 메모리셀의 고착고장, 천이고장, ANPSFs(Active Neighborhood PSF), PNPSFs(Passive Neighborhood PSF), 그리고 SNPSFs(Static Neighborhood PSF)를 검출할 수 있다. 가능한 현재 사용되는 기본 소자를 사용하여 부가 회로의 면적을 줄이도록 하였다.

For the effective test of highly densed RAMs, the detecting algorithm of PSFs is proposed and a test circuit is designed as an additive circuit inside a memory chip, which is often called a BIST(Built-In Self Test) circuit. With 128 gray codes and 4 basic cells for the tiling, read and write operations are performed to entire column lines in each row.

If there is an error, it is detected simultaneously (because the outputs of error detecting circuits are connected with output pins) and the algorithm covers Stuck-at Faults, Transition Faults, ANPSFs(Static Neighborhood PSF).

Furthermore, the area for the BIST circuit can be minimized by using the existing components.

For the effective test of highly densed RAMs, the detecting algorithm of PSFs is proposed and a test circuit is designed as an additive circuit inside a memory chip, which is often called a BIST(Built-In Self Test) circuit. With 128 gray codes and 4 basic cells for the tiling, read and write operations are performed to entire column lines in each row.

If there is an error, it is detected simultaneously (because the outputs of error detecting circuits are connected with output pins) and the algorithm covers Stuck-at Faults, Transition Faults, ANPSFs(Static Neighborhood PSF).

Furthermore, the area for the BIST circuit can be minimized by using the existing components.