Backplane Interconnect 테스트를 위한 BIST 회로 설계

Abstract

Backplane은 여러 개의 보드(board), 즉 부시스템(sub-system) 간의 연결을 제공하는 전형적인 방법이다. 각 보드들은 Backplane의 Interconnect를 통하여 서로 신호를 교환한다. Backplane의 고장(fault)은 전체 시스템을 오동작하게 한다. Interconnect의 고장은 보드를 제거하거나, 교체, 또는 추가할 경우에 발생될 수 있다. Backplane Interconnect 테스트는 이러한 고장을 검출하여 시스템의 동작을 검증할 수 있는 중요한 과정이다. 본 연구에서는 BIST(Built-In Self-Test) 기법을 채택하여 테스트 장비의 사용으로 발생될 수 있는 비용을 최소화하였고 Interconnect의 고장을 자동으로 검출할 수 있게 하였다. 고장 검출을 위해 N+1 알고리즘을 하드웨어로 구성하여 다중 고장에 대해 완전한 검출이 이루어질 수 있도록 설계하였다. 그리고 고장 점검 및 진단을 위한 테스트 패턴 주입을 위해 보드 수준의 테스트에 사용되는 IEEE Std 1149.1 Boundary Scan Architecture 기법을 적용하였다. 시스템 수준에서는 시스템의 다양한 사양에 적용이 용이하도록 설계하는 ?痼? 중요하다. 본 논문의 BIST 회로는 카운터 크기의 변경만으로 전체 회로의 수정 없이 적용될 수 있게 하였다.

Backplane is a well-known method for inter-board connections. These boards are usually plugged into the backplane of the communication systems and are used to exchange signal with each other via backplane interconnects. Since the backplane is the main communication link, its error free operation is crucial to the system's operability. Generally, faults can be introduced whenever a board is removed or replaced or added. This backplane interconnect testing is a very important process to verify the operation of system. In this paper, the BIST(Byilt-In Self Test)methodology is adopted to minimize the cost of test equipments and to detect faults automatically. This BIST circuit was implemented using the N+1 algorithm to detect multiple faults and the IEEE Std. 1149.1 Boundary Scan Architecture methodology to inject test patterns. At the system level, the BIST circuit must be designed to be easily modified for the potential system configuration. By changing the size of counter only, the proposing BIST circuit can be adapted to many types of system configurations without any modification of entire system.

Backplane is a well-known method for inter-board connections. These boards are usually plugged into the backplane of the communication systems and are used to exchange signal with each other via backplane interconnects. Since the backplane is the main communication link, its error free operation is crucial to the system's operability. Generally, faults can be introduced whenever a board is removed or replaced or added. This backplane interconnect testing is a very important process to verify the operation of system. In this paper, the BIST(Byilt-In Self Test)methodology is adopted to minimize the cost of test equipments and to detect faults automatically. This BIST circuit was implemented using the N+1 algorithm to detect multiple faults and the IEEE Std. 1149.1 Boundary Scan Architecture methodology to inject test patterns. At the system level, the BIST circuit must be designed to be easily modified for the potential system configuration. By changing the size of counter only, the proposing BIST circuit can be adapted to many types of system configurations without any modification of entire system.