CPL을 이용한 DCT 프로세서의 설계

Abstract

DCT(Discrete Cosine Transform)는 정지화상용 JPEG(Joint Picture Experts Group)규격과 MPEG(Moving Picture Experts Group)규격 등에 널리 사용되기 때문에 DCT를 하나의 칩으로 개발하는 것은 영상 압축 시스템에 있어서 매우 중요하다.

본 연구에서는 DCT 프로세서를 CPL(Complementary Pass-Transistor Logic)로 구성하여 크기와 속도를 개선하도록 하였다. 특히 덧셈기 회로에서 CPL을 사용하였는데, CPL은 상호보완(complementary) 입력/출력, nMOS pass-transistor 회로, CMOS 출력 반전기로 구성한다. CPL로 구성한 전가산기는 일반 CMOS로 구성한 전가산기보다 트랜지스터의 개수가 30% 감소되고 속도도 2배 정도의 개선 효과를 가진다. 따라서 전체 크기를 줄일 수 있고 속도를 개선할 수 있다.

A high speed signal processing is needed in multimedia due to enormous data. So, we have to use image compression technique. The DCT (Discrete Cosine Transform) has been widely used, because it is not only adopted in JPEG (Joint Picture Experts Group) and MPEG (Moving Picture Experts Group) but also effective in image compression. So, we can achieve high speed and reduction of size by developing the chip which implements DCT speedily. This paper improves speed and reduces processor chip size by adopting the CPL (Complementary Pass-Transistor Logic) in implementing the DCT processor. Especially, the CPL will be used in adder circuits. This CPL will be composed of complementary input/output, nMOS pass-transistor circuits, CMOS output inverter. The number of transistors of full adder constructed by CPL is less than that of full adder constructed by general techniques, also it is two times faster than other circuits. The total designed circuits will be simulated and fabricated by one chip. We expect that this total design will be used in developing the high performance image processing processor.

A high speed signal processing is needed in multimedia due to enormous data. So, we have to use image compression technique. The DCT (Discrete Cosine Transform) has been widely used, because it is not only adopted in JPEG (Joint Picture Experts Group) and MPEG (Moving Picture Experts Group) but also effective in image compression. So, we can achieve high speed and reduction of size by developing the chip which implements DCT speedily. This paper improves speed and reduces processor chip size by adopting the CPL (Complementary Pass-Transistor Logic) in implementing the DCT processor. Especially, the CPL will be used in adder circuits. This CPL will be composed of complementary input/output, nMOS pass-transistor circuits, CMOS output inverter. The number of transistors of full adder constructed by CPL is less than that of full adder constructed by general techniques, also it is two times faster than other circuits. The total designed circuits will be simulated and fabricated by one chip. We expect that this total design will be used in developing the high performance image processing processor.