프로그래머블 디지탈 필터의 설계 및 제작

Abstract

디지탈필터의 계수 및 종류에 무관한 고속 디지탈 필터를 처리하기 위한 programmable processor를 설계하고, 이의 효율을 산출하였다.

μP를 사용하므로 필터변동에 따라 프로그램으로 처리하여 flexibility를 유지하면서 TTL logic으로 프로세서 처리속도를 실시간에서 가능하도록 하였다.

Sampling frequency, f?=1/(number of instruction)*(cycle time)으로 cycle time에 반비례한다. 구성된 회로의 cycle time은 210ns로, IC로 제작되면 더욱 단축가능하고 일반μP 와 직접연결이 가능하다. 제안된 프로세서는 기존회로보다 2배의 증가된 효율을 얻었고, 간단한 회로구성이 가능하다.

The digital signal processing requires high speed computation capability in real time processing.

Many dedicated hardware processors are based on pre-calculated coefficients or its unique architecture.

This paper describes the architecture of programmable digital filter with a distributed configuration using μP 8086.

The processor accepts the microprogram from the μP to execute the algorithm. The sequence of microprogram is executed sequentially in order to simplify the processor circuits, and muliplication is replaced by the series of addition, substraction and shift operations simultaneously.

The experimental results offer better efficiency than other multiplier in practical bit size.

This structure provides a good flexibility through, μP and high speed computation with TTl logic family.

The cycle time is 210ns so multichannel processing could be implemented depending on the length of program.

The digital signal processing requires high speed computation capability in real time processing.

Many dedicated hardware processors are based on pre-calculated coefficients or its unique architecture.

This paper describes the architecture of programmable digital filter with a distributed configuration using μP 8086.

The processor accepts the microprogram from the μP to execute the algorithm. The sequence of microprogram is executed sequentially in order to simplify the processor circuits, and muliplication is replaced by the series of addition, substraction and shift operations simultaneously.

The experimental results offer better efficiency than other multiplier in practical bit size.

This structure provides a good flexibility through, μP and high speed computation with TTl logic family.

The cycle time is 210ns so multichannel processing could be implemented depending on the length of program.