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A quantitative approach for trap analysis between Al0.25Ga0.75N and GaN in high electron mobility transistors

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Alternative Title
Quantitative Trap Analysis of Interface between Al0.25Ga0.75N and GaN in High-Electron-Mobility-Transistors
Abstract
The characteristics of traps between the Al0.25Ga0.75N barrier layer and the GaN channel in a high-electron-mobility-transistors (HEMTs) were investigated. The interface traps at the Al0.25Ga0.75N/GaN interface as well as the border traps were experimentally analyzed, because the Al0.25Ga0.75N barrier layer functions as a dielectric owing to its high dielectric constant. The interface trap density Dit and border trap density Nbt were extracted from a long-channel field-effect transistor (FET), conventionally known as a FATFET structure, via frequency-dependent capacitance?voltage (C?V) and conductance?voltage (G?V) measurements. The minimum Dit value extracted by the conventional conductance method was 2.5 × 1012 cm-2·eV-1, which agreed well with the actual transistor subthreshold swing of around 142 mV·dec-1. The border trap density Nbt was also extracted from the frequency-dependent C?V characteristics using the distributed circuit model, and the extracted value was 1.5 × 1019 cm-3·eV-1. Low-frequency (1/f) noise measurement provided a clearer picture of the trapping-detrapping phenomena in the Al0.25Ga0.75N layer. The value of the bulk trap density extracted using the carrier-number-fluctuation (CNF) model was 1.3 × 1019 cm-3·eV-1, which is of a similar level to the extracted value of the border trap density.

Introduction
Recently, GaN-based high-electron-mobility-transistors (HEMTs) have gained considerable attention because of their outstanding material properties and device performance, including power and RF applications up to the sub-terahertz regime1,2,3. These advantageous properties and performance are attributable mainly to the high quality of the epitaxial layer comprising the AlxGa1-xN barrier layer and the GaN channel, which causes the formation of two-dimensional electron gas (2DEG) on top of Si, sapphire, and SiC substrates4,5. The quality of the AlxGa1-xN/GaN interface is crucial to improvement of the carrier transport in the channel during device operation6,7. In addition to the performance of AlGaN/GaN HEMTs, their reliability is an ongoing topic of research that requires examination of a variety of factors. Most of the reliability issues are related to the AlGaN layer, which is the surface layer in the gate-to-drain access region and contains deep-level traps8. These issues become more critical in deeply scaled transistors for high-frequency applications. Most previous research on the reliability of AlGaN/GaN HEMTs focused mainly on the surface traps in the access region and on their passivation using dielectric materials9,10. Plasma treatment was also utilized to decrease these deep-level traps in the AlGaN barrier layer11. Characterization of interface traps and deep-level bulk traps is important for
Author(s)
김재무김태우박경호신기용신주원아미르 왈리드조주영Hideaki MatsuzakiHiroki SugiyamaTakuya HoshiTakuyaTsutsumi
Issued Date
2021
Type
Article
Keyword
CapacitanceConductanceDielectric constantFrequency dependenceMobilityTransistorsTrapsVoltage
DOI
10.1038/s41598-021-01768-4
URI
https://oak.ulsan.ac.kr/handle/2021.oak/9064
https://ulsan-primo.hosted.exlibrisgroup.com/primo-explore/fulldisplay?docid=TN_cdi_doaj_primary_oai_doaj_org_article_fab21a9fee9a4362ab6f717d38ac996d&context=PC&vid=ULSAN&lang=ko_KR&search_scope=default_scope&adaptor=primo_central_multiple_fe&tab=default_tab&query=any,contains,A%20quantitative%20approach%20for%20trap%20analysis%20between%20Al0.25Ga0.75N%20and%20GaN%20in%20high%20electron%20mobility%20transistors&offset=0&pcAvailability=true
Publisher
SCIENTIFIC REPORTS
Location
독일
Language
영어
ISSN
2045-2322
Citation Volume
11
Citation Number
1
Citation Start Page
22401
Citation End Page
22401
Appears in Collections:
Engineering > IT Convergence
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